Consider the digital circuit shown below with two input lines A and B, two select lines S0 and S1, and an output line Y. The blocks Q and M represent active high 2:4 decoder and 4-to-1 multiplexer, respectively. Out of 16 possible input combinations, the number of combinations that produce Y=1 is ____________. (*answer in integer*) *Note:* One input combination is an instance of [A B S1 S0].

Figure for GATE CSE 2026 | Set 2 | Question 59

Numerical answer

Your answer

Source: GATE CSE 2026 Set 2 (CS2), IIT Guwahati. Official question paper.

GATE CSE 2025 | Set 2 | Question 31

Combinational Circuits·Boolean Algebra & K-map

MSQ1 mark

Consider the following logic circuit diagram. Which is/are the CORRECT option(s) for the output function

F

Figure for GATE CSE 2025 | Set 2 | Question 31

One or more correct

Source: GATE CSE 2025 Set 2 (CS2), IIT Roorkee. Official question paper.

GATE CSE 2024 | Set 1 | Question 28

Combinational Circuits

MSQ1 mark

Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays. Which of the following statements about the circuit is/are CORRECT?

Figure for GATE CSE 2024 | Set 1 | Question 28

One or more correct

Source: GATE CSE 2024 Set 1 (CS1), IISc Bengaluru. Official question paper.

GATE CSE 2024 | Set 1 | Question 64

Combinational Circuits

NAT2 marks

Consider a digital logic circuit consisting of three 2-to-1 multiplexers M1, M2, and M3 as shown below. X1 and X2 are inputs of M1. X3 and X4 are inputs of M2. A, B, and C are select lines of M1, M2, and M3, respectively. For an instance of inputs X1=1, X2=1, X3=0, and X4=0, the number of combinations of A, B, C that give the output Y=1 is __________

Figure for GATE CSE 2024 | Set 1 | Question 64

Numerical answer

Your answer

Source: GATE CSE 2024 Set 1 (CS1), IISc Bengaluru. Official question paper.

GATE CSE 2024 | Set 2 | Question 50

Combinational Circuits·Boolean Algebra & K-map

MSQ2 marks

Consider 4-variable functions

f_1, f_2, f_3, f_4

expressed in sum-of-minterms form as given below.

\begin{aligned} f_1 &= \textstyle\sum(0,2,3,5,7,8,11,13) \\ f_2 &= \textstyle\sum(1,3,5,7,11,13,15) \\ f_3 &= \textstyle\sum(0,1,4,11) \\ f_4 &= \textstyle\sum(0,2,6,13) \end{aligned}

With respect to the circuit given above (see figure), which of the following options is/are CORRECT?

Figure for GATE CSE 2024 | Set 2 | Question 50

One or more correct

Source: GATE CSE 2024 Set 2 (CS2), IISc Bengaluru. Official question paper.

GATE CSE 2023 | Question 21

Sequential Circuits·Combinational Circuits

MCQ1 mark

The output of a 2-input multiplexer is connected back to one of its inputs as shown in the figure. Match the functional equivalence of this circuit to one of the following options.

Single correct

Answer key coming soon

Source: GATE CSE 2023, IIT Kanpur. Official question paper.

GATE CSE 2023 | Question 44

Combinational Circuits

MCQ2 marks

A Boolean digital circuit is composed using two 4-input multiplexers (M1 and M2) and one 2-input multiplexer (M3) as shown in the figure. X0–X7 are the inputs of the multiplexers M1 and M2 and could be connected to either 0 or 1. The select lines of the multiplexers are connected to Boolean variables A, B and C as shown. Which one of the following set of values of (X0, X1, X2, X3, X4, X5, X6, X7) will realise the Boolean function

\overline{A} + \overline{A}\cdot\overline{C} + A\cdot\overline{B}\cdot C

Single correct

Answer key coming soon

Source: GATE CSE 2023, IIT Kanpur. Official question paper.

GATE CSE 2022 | Question 40

Combinational Circuits

MCQ2 marks

Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X, either from S or from R. S is a 1024-word memory segment and R is a 32-word register file. Based on the value of mode bit M, T selects an input word to load in X. P and Q interface with the corresponding bits in the code word to choose the addressed word. Which one of the following represents the functionality of P, Q, and T?

Single correct

Answer key coming soon

Source: GATE CSE 2022, IIT Kharagpur. Official question paper.

GATE CSE 2021 | Set 2 | Question 5

Combinational Circuits·Boolean Algebra & K-map

MCQ1 mark

Which one of the following circuits implements the Boolean function given below?

f(x, y, z) = m_0 + m_1 + m_3 + m_4 + m_5 + m_6,

where

m_i

is the

i^{th}

minterm. (The four circuits are shown in the figure.)

Figure for GATE CSE 2021 | Set 2 | Question 5

Single correct

Answer key coming soon

Source: GATE CSE 2021 Set 2 (CS2), IIT Bombay. Official question paper.

GATE CSE 2020 | Question 19

Combinational Circuits

NAT1 mark

A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is _________.

Numerical answer

Your answer

Answer key coming soon

Source: GATE CSE 2020, IIT Delhi. Official question paper.

GATE CSE 2020 | Question 20

Combinational Circuits·Cache & Memory Hierarchy

NAT1 mark

If there are

m

input lines and

n

output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of

m + n

is ____.

Numerical answer

Your answer

Answer key coming soon

Source: GATE CSE 2020, IIT Delhi. Official question paper.

GATE CSE 2020 | Question 28

Combinational Circuits·Boolean Algebra & K-map

MCQ2 marks

Consider the Boolean function

z(a, b, c)

(see the circuit in the figure). Which one of the following minterm lists represents the circuit given above?

Single correct

Answer key coming soon

Source: GATE CSE 2020, IIT Delhi. Official question paper.

GATE CSE 2019 | Question 2

Cache & Memory Hierarchy·Combinational Circuits

MCQ1 mark

The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by

A_{15}

A_0

. What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?

Single correct

Source: GATE CSE 2019, IIT Madras. Official question paper and answer key.

GATE CSE 2019 | Question 50

Combinational Circuits·Boolean Algebra & K-map

NAT2 marks

What is the minimum number of 2-input NOR gates required to implement a 4-variable function expressed in sum-of-minterms form as

f = \Sigma(0, 2, 5, 7, 8, 10, 13, 15)

? Assume that all the inputs and their complements are available.

Numerical answer

Your answer

Source: GATE CSE 2019, IIT Madras. Official question paper and answer key.

GATE CSE 2017 | Set 1 | Question 9

Combinational Circuits·Number Representation

MCQ1 mark

When two 8-bit numbers

A_7 \cdots A_0

and

B_7 \cdots B_0

in 2's complement representation (with

A_0

and

B_0

as the least significant bits) are added using a ripple-carry adder, the sum bits obtained are

S_7 \cdots S_0

and the carry bits are

C_7 \cdots C_0

. An overflow is said to have occurred if

Single correct

Answer key coming soon

Source: GATE CSE 2017 Set 1, IIT Roorkee. Official question paper.

GATE CSE 2017 | Set 1 | Question 21

Boolean Algebra & K-map·Combinational Circuits

NAT1 mark

Consider the Karnaugh map given below, where X represents "*don't care*" and blank represents 0.

\begin{array}{c|cccc} dc \backslash ba & 00 & 01 & 11 & 10 \\ \hline 00 & & X & X & \\ 01 & 1 & & & X \\ 11 & 1 & & & 1 \\ 10 & & X & X & \end{array}

Assume for all inputs

(a, b, c, d)

, the respective complements

(\bar{a}, \bar{b}, \bar{c}, \bar{d})

are also available. The above logic is implemented using 2-input NOR gates only. The minimum number of gates required is ________.

Numerical answer

Your answer

Answer key coming soon

Source: GATE CSE 2017 Set 1, IIT Roorkee. Official question paper.

GATE CSE 2016 | Set 1 | Question 30

Combinational Circuits

MCQ2 marks

Consider the two cascaded 2-to-1 multiplexers as shown in the figure. The minimal sum of products form of the output

X

Figure for GATE CSE 2016 | Set 1 | Question 30

Single correct

Answer key coming soon

Source: GATE CSE 2016 Set 1, IISc Bengaluru. Official question paper.

GATE CSE 2016 | Set 1 | Question 33

Combinational Circuits

MCQ2 marks

Consider a carry lookahead adder for adding two

n

-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is

Single correct

Answer key coming soon

Source: GATE CSE 2016 Set 1, IISc Bengaluru. Official question paper.

GATE CSE 2016 | Set 2 | Question 7

Combinational Circuits·Number Representation

NAT1 mark

Consider an eight-bit ripple-carry adder for computing the sum of

A

and

B

, where

A

and

B

are integers represented in 2's complement form. If the decimal value of

A

is one, the decimal value of

B

that leads to the longest latency for the sum to stabilize is ________.

Numerical answer

Your answer

Answer key coming soon

Source: GATE CSE 2016 Set 2, IISc Bengaluru. Official question paper.

GATE CSE 2015 | Set 2 | Question 65

Combinational Circuits

NAT2 marks

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is _____.

Numerical answer

Your answer

Source: GATE CSE 2015 Set 2, IIT Kanpur. Official question paper and answer key.

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