GATE CSE previous year questions · Computer Organization & Architecture

Pipelining

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Pipelining (Computer Organization & Architecture): GATE CSE PYQs | PYQ Hub

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GATE CSE 2026 | Set 1 | Question 16

Pipelining

MCQ1 mark

Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

Single correct

GATE CSE 2024 | Set 2 | Question 31

Pipelining

MSQ1 mark

An instruction format has the following structure: Instruction Number: Opcode destination reg, source reg-1, source reg-2 Consider the following sequence of instructions to be executed in a pipelined processor:

I1: DIV R3, R1, R2
I2: SUB R5, R3, R4
I3: ADD R3, R5, R6
I4: MUL R7, R3, R8

Which of the following statements is/are TRUE?

One or more correct

GATE CSE 2015 | Set 2 | Question 53

Pipelining

NAT2 marks

Consider the sequence of machine instructions given below:

MUL  R5, R0, R1
DIV  R6, R2, R3
ADD  R7, R5, R6
SUB  R8, R7, R4

In the above sequence, R0 to R8 are general purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perform Operation (PO) and (4) Write back the result (WB). The IF, OF and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD or SUB instruction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is _____.

Numerical answer

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Pipelining

Pipelining

Year

GATE CSE 2026 | Set 1 | Question 16

GATE CSE 2026 | Set 1 | Question 60

GATE CSE 2026 | Set 2 | Question 57

GATE CSE 2025 | Set 2 | Question 56

GATE CSE 2024 | Set 1 | Question 30

GATE CSE 2024 | Set 1 | Question 55

GATE CSE 2024 | Set 2 | Question 31

GATE CSE 2024 | Set 2 | Question 58

GATE CSE 2023 | Question 33

GATE CSE 2022 | Question 61

GATE CSE 2021 | Set 1 | Question 53

GATE CSE 2021 | Set 2 | Question 53

GATE CSE 2020 | Question 43

GATE CSE 2018 | Question 50

GATE CSE 2017 | Set 1 | Question 50

GATE CSE 2016 | Set 1 | Question 32

GATE CSE 2016 | Set 2 | Question 30

GATE CSE 2016 | Set 2 | Question 33

GATE CSE 2015 | Set 1 | Question 55

GATE CSE 2015 | Set 2 | Question 53

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