A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?

Figure for GATE CSE 2025 | Set 1 | Question 27

One or more correct

Source: GATE CSE 2025 Set 1 (CS1), IIT Roorkee. Official question paper.

GATE CSE 2025 | Set 2 | Question 61

Other / Removed from syllabus

NAT2 marks

An application executes

6.4 \times 10^8

number of instructions in 6.3 seconds. There are four types of instructions, the details of which are given in the table. The duration of a clock cycle in nanoseconds is _________. (rounded off to one decimal place)

\begin{array}{|l|c|c|} \hline \text{Instruction type} & \text{Clock cycles required per instruction (CPI)} & \text{Number of instructions executed} \\ \hline \text{Branch} & 2 & 2.25 \times 10^8 \\ \text{Load} & 5 & 1.20 \times 10^8 \\ \text{Store} & 4 & 1.65 \times 10^8 \\ \text{Arithmetic} & 3 & 1.30 \times 10^8 \\ \hline \end{array}

Numerical answer

Your answer

Source: GATE CSE 2025 Set 2 (CS2), IIT Roorkee. Official question paper.

GATE CSE 2016 | Set 1 | Question 9

Other / Removed from syllabus

NAT1 mark

A processor can support a maximum memory of 4 GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least ________ bits.

Numerical answer

Your answer

Answer key coming soon

Source: GATE CSE 2016 Set 1, IISc Bengaluru. Official question paper.

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