I/O Interface

Single correct

• ABoth S1 and S2 are true
• BBoth S1 and S2 are false
• CS1 is true and S2 is false
• DS1 is false and S2 is true

Single correct

• A(iii), (i), (ii)
• B(i), (iii), (ii)
• C(i), (ii), (iii)
• D(iii), (ii), (i)

Single correct

• AIn the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle
• BFor bulk data transfer, the burst mode of DMA has a higher throughput than the cycle stealing mode
• CProgrammed I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism
• DThe CPU can start executing an interrupt service routine faster with vectored interrupts than with non-vectored interrupts

Single correct

• A2,56,000
• B3,200
• C25,60,000
• D32,000

Numerical answer

Answer key coming soon

Single correct

• ADMA based I/O transfer
• BInterrupt driven I/O transfer
• CPolling based I/O transfer
• DProgrammed I/O transfer

Answer key coming soon

Numerical answer

Answer key coming soon

Single correct

• AI and II only
• BI and IV only
• CI and III only
• DIII only

Answer key coming soon

Single correct

• AQPTRS
• BPTRSQ
• CTRPQS
• DQTPRS

Numerical answer

Answer key coming soon

Numerical answer

Single correct

• AInstruction fetch
• BOperand fetch
• CConditional branch
• DInitiation of interrupt service

Answer key coming soon

Single correct

• AInterrupt from Hard Disk
• BInterrupt from Mouse
• CInterrupt from Keyboard
• DInterrupt from CPU temperature sensor

Answer key coming soon

      Initialize the address register
      Initialize the count to 500
LOOP: Load a byte from device
      Store in memory at address given by address register
      Increment the address register
      Decrement the count
      If count != 0 go to LOOP

Single correct

• A3.4
• B4.4
• C5.1
• D6.7

Answer key coming soon