GATE CSE previous year questions · Digital Logic

Sequential Circuits

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GATE CSE 2026 | Set 1 | Question 37

MCQ2 marks

Consider a 2-bit saturating up/down counter that performs the saturating up count when the input

P

is 0, and the saturating down count when

P

is 1. The Next State table of the counter is as shown. The counter is built as a synchronous sequential circuit using D flip-flops.

\begin{array}{|c|cc|cc|} \hline \text{Input } P & \text{Current } Q_1 & \text{Current } Q_0 & \text{Next } Q_1^+ & \text{Next } Q_0^+ \\ \hline 0 & 0 & 0 & 0 & 1 \\ 0 & 0 & 1 & 1 & 0 \\ 0 & 1 & 0 & 1 & 1 \\ 0 & 1 & 1 & 1 & 1 \\ 1 & 0 & 0 & 0 & 0 \\ 1 & 0 & 1 & 0 & 0 \\ 1 & 1 & 0 & 0 & 1 \\ 1 & 1 & 1 & 1 & 0 \\ \hline \end{array}

Which one of the following options corresponds to the expressions for the inputs of the D flip-flops,

D_1

and

D_0

?

Single correct

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